Memory systems can employ memory devices to store and access information. The memory devices can include volatile memory devices, non-volatile memory devices, or a combination device. Memory devices, such as dynamic random-access memory (DRAM), can utilize electrical energy to store and access data. For example, the memory devices can include Double Data Rate (DDR) RAM devices that implement DDR interfacing scheme (e.g., DDR4, DDR5, etc.) for high-speed data transfer.
FIG. 1 illustrates a block diagram of a memory device 100 (e.g., a DRAM device) that utilize electrical energy to store and access data. For example, the memory device 100 can include memory banks 102 that are organized/configured according to one or more bank groups 104. Each of the bank groups 102 can include a set of two or more memory banks 102. In some embodiments, each of the bank groups 104 can include a set of four or eight memory banks 102.
The memory device 100 can further include an input/output (I/O) circuit 106 configured to communicate data (e.g., DQ, RDQS, DBI, DMI, etc.), command, and/or address signals. In some embodiments, the I/O circuit 106 can include a first set of data I/Os 112 (e.g., pads/receivers for upper data (DQs <15:8>)), a second set of data I/Os 114 (e.g., pads/receivers for lower data (DQ <7:0>)), etc. For example, the memory device 100 may communicate the data in units of 16 or 32 bits. The first data I/Os 112 can communicate an upper portion (e.g., an upper nibble, an upper byte, an upper word/half, etc.). The second data I/Os 114 can communicate a lower portion (e.g., a lower nibble, a lower byte, a lower word/half, etc.). The terms “upper” and “lower” can correspond to the bytes (or 8 data set). For X4/X8 configuration, the lower byte can be DQ<3:0> or DQ<7:0> are used (while the upper bytes DQ<15:8> are not used externally or internally). For X16 configuration, both upper bytes and lower bytes will be used at the same time. In Read or Write operations, there are certain defined burst length (e.g., BL=8 means 8 data bits are written in or read out) for each data set. The Read and Write operations are reversed where Read uses Parallel To Serial FIFO to clock out 8 bits serially whereas Write uses Serial To Parallel latches to line up data parallelly. The handshake of external control and internal control helps to make the bi-directional data propagation back and forth between Array and IO.
In some embodiments, the data I/Os can include data masks, such as an upper data mask (UDM) and upper data strobe (UDQS/UDQSF) for the first data I/Os 112 and a lower data mask (LDM) and lower data strobe (LDQS/LDQSF) for the second data I/Os 114, used to cover non-overlapping portions of the data unit. The memory device 100 can use the data masks to cover a portion of the data and keep the portion untouched, while writing to the uncovered portion of the data.
In some embodiments, the I/O circuit 106 can include a set of command and/or address pads 118. The command/address pads 118 can be configured to communicate/receive commands (e.g., read/write/erase commands from a controller/processor) and/or addresses associated with the data.
The communicated data, command, address, etc. can be routed to/from the corresponding location (e.g., the particular/designated set of data cells). In some embodiments, the I/O circuit 106 can include a center hub 122, bank logics 124, etc. The center hub 122 can be configured to perform the bank group or group-level control. The bank logic circuits 124 can be configured to perform the bank-level control. The center hub 122, the bank logic circuitry 124, etc. can include a set of drivers (e.g., one-directional drivers and/or bi-directional drivers) for communicating the data with the memory banks 102.
The memory device 100 can correspond to a wide I/O device configured to process relatively large amounts of data to keep up with increasing computer/processor performances. Further, the memory device 100 (e.g., DRAM) can have/support various I/O configurations, such as X4, X8, X16, etc. The I/O configurations can include multiple sets of data buses that connect the center hub 122 and the data I/Os. For example, the center hub 122 can be connected (e.g., direct connection) to the first data I/Os 112 through a first data bus 132. Also, the center hub 122 can be similarly connected to the second data I/Os 114 through a second data bus 134. In some embodiments (e.g., X16 configurations), the first data bus 132 and the second data bus 134 can each include 72 tracks for communicating data/information/bits between the I/Os and the center hub 122. Accordingly, a combined bus (e.g., between the center hub 122 and the second data I/Os 114) can include 144 tracks.
For communicating/processing the information, the memory device 100 can include one or more circuit components (e.g., drivers, receiver, logic, etc.) for each I/O track. Further, in order to support the various I/O configurations, the memory device 100 can include additional circuit components (e.g., drivers, receiver, logic, etc.) for each I/O track. While each processing circuit component requires die space, the additional circuit components (e.g., configured to support the various I/O configurations) further complicate the data management and increase the physical size of the memory device 100.
With technological advancements in other areas and increasing applications, the market is continuously looking for faster, smaller, and more efficient devices. To meet the market demand, the semiconductor devices are being pushed to the limit. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the desire to differentiate products in the marketplace, it is increasingly desirable that answers be found to these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater pressure to find answers to these problems.